1. Field of the Invention
The invention relates to semiconductor circuits, and in particular to a clock receiver automatically capable of calibrating phase offset caused by inconsistency in duty cycles between the complementary clocks.
2. Description of the Related Art
Generally, dynamic random access memories (DRAMs) use a clock receiving unit to receive a pair of complementary clocks (such as VCLK and /VCLK) and accordingly generates a main clock (such as MCLK) for internal circuits. However, the duty cycles of the complementary clocks are inconsistent because of element mismatch, temperature or other factors.
As shown in FIG. 1A, the duty cycle of the clock VCLK is larger than that of the clock /VCLK, such that cross points CP3 and CP4 of the two clocks VCLK and /VCLK are generated at times t1 and t3, respectively rather than at predetermined times t2 and t4, respectively. Namely, the cross time of the two clocks is advanced because of inconsistency of the duty cycles thereof. On the contrary, the cross time of the two clocks is delayed as shown in FIG. 1B, when the duty cycle of the clock VCLK is smaller than that of the clock /VCLK. Namely, the clock receiving unit in the DRAMs receive a distorted clock MCLK0 rather than the predetermined main clock MCLK0. Thus, the clocks MCLK0 and MCLK1 have a phase offset affecting margin of the clocks in the internal circuits in the DRAMs.